Slope generators (also referenced as waveform, ramp or sawtooth wave generators) are used in several applications for generating signals with a controllable slope. Typically, a current integrating capacitor is charged/discharged to produce a ramp signal.
FIG. 1 depicts a slope generator 10 as known in the art, e.g. a 1DB6 ("Snake") Slope Generator IC as used in the Hewlett-Packard HP8112A. The slope generator 10 comprises a fixed connected current source 20 providing a charge current I_up to load a ramp-capacitor C_ramp from a voltage low level V_l to a voltage high level V_h as output voltage V_out at a node 25. A current source 30 switchable by a current switch 40 (consisting of transistors Q1 and Q2) provides a current I_dn (whereby I_dn&gt;I_up) to discharge the ramp-capacitor C_ramp from voltages V_h to V_l with a discharge current of I_dn-I_up. An input pulse V_in with fast edges at the current switch 40 controls the coupling of the current source 30 to the ramp-capacitor C_ramp. A low-level of the input pulse V_in switches on I_dn and a high level of the input pulse V_in switches off I_dn.
With the current I_dn being turned off, the ramp-capacitor C_ramp will be charged with a constant current I_up (thus generating a rising slope with the slew rate of dV/dt=I_up/C_ramp) until a clamping diode D2 (coupled to a clamping voltage V_cl_h) is taking over this current, thus stopping the charging. With I_dn being turned on, the ramp-capacitor C_ramp will be discharged with a constant current I_dn-I_up (thus generating a falling slope with the slew rate of dV/dt=-(I_dn-I_up)/C_ramp) until a clamping diode D1 (coupled to a clamping voltage V_cl_l) is taking over this current, thus stopping the discharging.
The voltage levels V_l and V_h of the output voltage V_out at the ramp node 25 of the ramp-capacitor C_ramp are derived from the clamping voltages V_cl_l and V_cl_h: EQU V.sub.-- l=V.sub.-- cl.sub.-- l(I_dn-I_up, T)-Vf.sub.-- D1(I_dn-I_up, T) (1a) EQU V.sub.-- h=V.sub.-- cl.sub.-- h(I_up, T)+Vf.sub.-- D2(I_up, T) (1b).
The clamping voltage V_cl_l and the forward voltage Vf_D1 at diode D1 are both dependent on the differences between the currents I_dn and I_up and on the temperature T. Accordingly, the clamping voltage V_cl_h and the forward voltage Vf_D2 at diode D2 are both dependent on the current I_up and the temperature T.
The time to charge the capacitor C_ramp and thus the rising time T_rise of the slope generator 10 is: ##EQU1##
Accordingly and with I_dn&gt;I_up, the time to discharge the capacitor C_ramp and thus the falling time T_fall of the slope generator 10 is: ##EQU2##
As apparent from equations (2) and (3), the timing of the slope generator 10 directly depends on the voltage levels V_h and V_l. Therefore, significant effort has to be spent to compensate the thermal and current dependency of the clamping diodes D1 and D2.
Another, even more serious disadvantage of the slope generator 10 of FIG. 1 is the capacitive loading by two clamping diodes (D1 and D2), thus limiting the minimum feasible ramp-capacitance C_ramp_eff, and accordingly, the minimum feasible transition times T_rise and T_fall. This is since the fastest slope (or transition time) is determined by the highest possible charging current and the lowest possible capacitance at the node 25, whereby the capacitance at the node 25 is determined by the capacitor C_ramp and parasitic capacitances. On the other hand, the parasitic capacitance of the clamping diodes D1 and D2 exhibits a strong dependency on the applied voltages, thus resulting in a negative impact on a desired linear slope. Since V_cl_l and V_cl_h represent low impedance nodes, the influence of parasitic capacitance of the clamping diodes D1 and D2 will add fully to the ramp capacitor C_ramp.